EXPERIENCE - EDUCATION - SKILLS - PERSONAL

EXPERIENCE:
Owner, t2design

• Client O: Lead a 3 person team to develop a spacecraft quality FPGA for a motor controller. The FPGA has 1553B command and telemetry interface, table lookup to drive stepper motor profiles, manual override and ADC housekeeping channels. Extensive documentation and verification environment was developed.
  
• Client N: Migration to a new foundry and improvement of synthesis environment for an ARM based ASIC which supported a tape subsystem. Moved the team to a top-down synthesis environment while acting as technical contact for the new foundry.
  
• Client M: Lead a 3 person team to develop a spacecraft quality FPGA for a motor controller. The FPGA had serial command and telemetry interface, automatic DC-brushless motor profiles and manual override methods. Extensive documentation and verification environment was required.
  
• Client L: Development of at-speed test vectors using Synopsys TetraMax Delay Fault ATPG. Succeeded in increasing the ASIC yield from ~75% to over 95%. Presenting a technical paper at SNUG San Jose 2002 "Using Limited Pin Testing with TetraMax for 1312 pin ASIC and other TMAX Fun" which included the details of the Delay Fault approach.
  
• Client K: Development of verification plan using Synopsys Vera language to validate a processor interface ASIC. The ASIC handled communication between the CPU, subsystem memory and other CPUs in a multiple processor system.
  
• Client J: Timing Analysis of legacy telecommunication design which was migrated from 1.5u to 0.25u technology. 
  
• Client I: Contributed to commercializing a telecommunication core based on the G.726 ADPCM specification. 
  
• Client H: Authored Xilinx Application Note titled "Re-Thinking Your Verification Strategies for Multi-Million Gate FPGAs." 
  
• Client G: Developed a test board which integrated Xilinx PCI core and bridge interfaces to several ATM chips. 
  
• Client F: Developed new methodology to migrate legacy Verilog HDL to support both VerilogXL and NCVerilog; involved integration of new data management system. Developed a new synthesis approach based on Synopsys Design Budgeter; presented technical paper at SNUG San Jose 2000 titled "ASIC Flow Engine for Timing Closure (AFETC), A Makefile Generator to Automate Design Budgeter Methodology." Contributed to the design of several functional modules. Responsible for RTL to Gates Synthesis and Layout Timing Closure of 870Kgate ASIC; presented technical paper at SNUG San Jose 2001 "Timing Closure of a 870Kgate + 3Mbit RAM, 0.20u-12mm Die in a 1312 Pin Package ASIC."
  
• Client E: Developed technique to produce unique FPGAs which interfaced to various imaging sensors using common HDL source. Created a test plan and a test bench to check for error conditions and design requirements.
  
• Client D: Responsible for repackaging four existing ASICs into one.  Added new features and extended the functionality of existing requirements. Involved in the project from many aspects: implementation, simulation, synthesis, chip route and completion of ASIC sign-off.
  
• Client C: Developing Synthesis and Simulation Libraries for full custom ASIC.
  Developed the overall test plan for the full chip to reduce test time.
  
• Client B: Developing methodology to migrate existing HDL-ASIC design into multiple FPGAs for emulation.
  Continued working with client to migrate the ASIC designs into FPGAs which included redesign of ASIC functionality to exploit FPGA architectures.
  
• Client A: ``Competitive Analysis of FPGA Back-End Tools."
  'The analysis consists of developing a criteria matrix (as web based forms), a decision matrix, and integrating three FPGA tools into a HDL through Synthesis design flow. Developed benchmark circuits to stress features of tools and architectures. Delivering a candid report on each vendor's tool performance on over 10 benchmark circuits.
   

Founder, Talcian Corporation

• Authored and delivered paper titled ``Using VHDL Abstract Data Types to Design a 3-D Graphics Pipeline'' at HP Design Supercon 97.
  
• Client D: Designed an FPGA to capture video data into a VRAM frame buffer. Developed a second FPGA to reformat the video data and write to a specialty display at 40MHz.
  
• Client C: Delivered VHDL Training Courses
  ranging from 5 day complete course to 1 day Xilinx and Synthesis seminars.
  
• Client B: Developed a process to migrate VHDL source and revision data from a workstation to a PC to support completion of a tape data reformatting ASIC.
  
• Client A: Developed Synthesis and Simulation Libraries for full custom ASIC. Developed the custom synthesis process. Authored multiple internal papers on the use of design and development tools. Papers include but are not limited to: RCS revision system, Client design data organization, Streamlining synthesis scripts, and Use of VHDL Libraries to organize a design.
   

Electrical Engineering Consultant

• Client A: Implemented VHDL test bench to verify system using ATM Utopia Level 1.
  

Ball Corporation

•  Sr. Project Leader.
  Identified, hired and managed a group of 12 engineers to complete the development of three ASIC designs for a 3-D graphic subsystem. The ASIC designs used a mixture of Behavioral VHDL, RTL VHDL and LSI macros. Responsible engineer for one of the three ASIC designs. Developed schedules, resource needs and budgets necessary to meet the customer schedule requirements. Developed a completion road map for prototypes and production grade ASICs. Managed design team which completed all three ASIC designs 294K, 270K and 92K gates in 10 calendar months with first pass success. Ball Real Time Imaging.
  
•  Sr. Design Engineer.
  Team member for development of next generation visual simulation hardware. Gained familiarity with PCI Bus, Xilinx FPGA and EPLD, RAMDAC, GUI Graphic chips, DRAM and VRAM. Designed a synchronous 40MHz back plane and clock distribution system for card to card interface. Authored documents describing module level specifications and theories of operation. Developed risk assessment data for the product including ASIC and PCB subsystem which covered: ASIC fabrication, ASIC testing and production using SCAN path, PCB fabrication using Chip On Tape and Ball Grid Array technologies, PCB testing using JTAG and system maintenance. Ball Imaging Products.
  
•  Staff EDA Support Engineer.
  Provided support to engineering staff as the in-house EDA application support engineer. Duties included: development of tools, support for design problems and design of a new EDA system to support management's budget constraints and the needs of departmental engineers. Developed a network system using PC-NFS and SUN workstations to support overall productivity of engineering department. Trained department team members. Ball Aerospace.
  
•  Design Engineer.
  Member of development team that designed a high resolution infrared imaging system. Implemented a custom DSP processor with input data in excess of 1 Gbps and frame throughput in excess of 4000 frames per second that interfaced to multiple array processors. Designed, simulated, fabricated, tested and integrated the system in less than a year. The three board system contained a total of 340 ACT, CMOS and F large-scale and medium-scale integrated circuits in addition to 30 programmable logic devices. Ball Aerospace.
  
•  Design Engineer.
  Part of a team that developed a remote data gathering and control system that transmitted test data to a computer via fiber optics. The system comprised of seven boards with custom serial and parallel buses including a 50MHz fiber optic bus. Developed analysis tools with EDA system to check overall fan-out of multiple family devices and to drive a third party wire-wrap process. Designed, fabricated, tested and integrated the system in less than 9 months. Ball Aerospace.
   

EDUCATION:

• B.S. Electrical Engineering, Colorado State University, Ft. Collins - 1983
  
• Continuing Education at University of Colorado; C programming and Technical Writing.
  
• EMI/EMC Grounding and Shielding, University of Missouri, 1988
   

References available by request.
 

Last Modified: 10/23/01 05:43 AM -0600