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Papers/Publications/Seminars
Synopsys User Group (SNUG) Boston 2001 - Papers available
September
TITLE: Using Limited Pin Testing with TetraMax for
1312 pin ASIC.
AUTHORS: Thomas D. Tessier, t2design Incorporated and
Roger Perry, StorageTek
Abstract: With pin counts of ASICs exceeding both
wafer and final package tester capabilities, foundries have turned to
using a subset of pins for testing. The use of Limited Pin Test (LPT)
requires engineers to alter traditional ATPG flows. In this paper we
outline our approach to using the TetraMax ATPG tool with the foundry
LPT guidelines. The foundry guidelines were in development during the
same time-frame as our ASIC design. We discuss how we solved issues
like; how to turn a TAP controller into just another Scan Ring; what to
do about all the unused inputs and finally what makes a good candidate
for scan ports. We used the WGL format as an output to our foundry.
Synopsys TetraMax has many WGL options. We optimize the options for our
design. We will provide a checklist of recommended practices and
question that users can ask themselves and the EDA vendors and Foundries
that support their ASIC.
TITLE: Timing Closure of a 870Kgate + 3 Mbit Ram,
0.20u-12mm die in a 1312 pin package ASIC.
AUTHORS: Thomas D. Tessier, t2design Incorporated and
Craig Buhlman, StorageTek
Abstract: Timing Closure has been the most pressing
issue facing ASIC design teams. It is well documented in the press that
timing closure is effecting a majority of the 0.25u and below ASICs. In
this paper we outline the issues we faced and how our design team solved
these problems to achieve timing closure. Due to the large number of RAMs
in our design, we found it necessary to use hierarchical place and route
approaches. The paper will outline what the design team perceived as a
solid use of currently available EDA tools (circa early 1999) coupled with
an automated flow, See SNUG SJ2000 paper; "ASIC Flow Engine for
Timing Closure (AFETC) a Makefile Generator to Automate Design Budgeter
Methodology." The proposed timing closure flow (plan) was to use
Avant Planet Floorplanner, Synopsys Floorplan Manager and Design Budgeter
with PrimeTime. We wil highlight our discovers of hour uour flow chice
affected timing closure. Finally we will detail the success we had at
achieving the goal of releasing the chip. We will provide a checklist of
recommended practices and question that users can ask themselves and the
EDA vendors and Foundries that support their ASIC.
Tools: PDEF Merge
- A tool to take in multiple PDEF files created by Avant! Apollo Router
and Merge them into one large PDEF file suitable for Synopsys Floorplan
Manager.
Shatter - A tool which will split large
netlists into multiple files but provide a script to reasemble them so
that Avant! Apollo does not complain when performing an ECO. The
module order needs to be the same as was orginally created for Apollo to
be happiest.
IPOFIX - The version of IPOFIX that we used
to upsize gates in our design. This version has all the array
indexes setup as #defines thus easier to modify based on your
design. I have successfully compiled this on SUN, HP and PC's using
the CYGWIN package from
RedHat.
TITLE: Re-thinking Your Verification Strategies
for Multimillion-gate FPGA.
AUTHOR: Thomas D. Tessier, t2design Incorporated
ABSTRACT: FPGA verification is essential for
successful time-to-market product delivery, and today’s million-gate
FPGAs require you to re-think your old strategies. So how do you alter
your verification techniques to meet today's high gate count requirements?
It depends on your background and experience.
TITLE: ASIC Flow Engine for Timing Closure
(AFETC) a Makefile Generator to Automate Design
Budgeter Methodology.
AUTHORS: Thomas D. Tessier, t2design
Incorporated and Mavin L. Anderson, StorageTek
ABSTRACT: In the DC98.08 tool release Synopsys
added the capability for the designer to develop top level constraints and
then flow them downward to the lower level blocks in a more uniform method
than the previous process of Characterize, Compile and Write (CCW). This
Synopsys tool is called the Design Budgeter. In order to flow the
constraints the designer must, at a minimum, run four invocations of DC on
each module. The first pass generates a GTECH DB. The second run develops
a baseline for estimation. Invocation three applies the actual constraints
to the blocks. The fourth pass does an incremental cleanup of the design.
It would be quite easy in a multiple person team environment for the
resulting net list to be incorrect with so many passes to manage. We chose
to manage our process flow with a script. Our Perl script was designed to
generate makefiles that automate the design flow. The use of the Perl
script combined with a solid data management system provides design groups
a repeatable and predictable flow from RTL to gates ready for layout.
Tools: Afetc - The perl
script which builds the makefiles.
Join us for a free hands on workshop that will expand your skills
and streamline your FPGA design process.
Using VHDL Abstract Data Types to Design a 3-D Graphics Pipeline
VIUF Fall Context -
Louisville Elementary onto the Internet -
How to get your elementary school wired to the internet.
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